4. Leg Control Board DesignHexotica - The Design and Implementation of a Small Walking Robot
The leg control board is an expansion board that is attached to the hardware control system described in the previous chapter. It provides an interface between the control system and the actual legs of the robot.
This section will discuss how various hardware devices on the leg control board work. The role of the leg control board is to:
- Provide an interface for the control system to read limit switches on the leg as digital data
- Convert analog data from potentiometers on the leg into digital data readable by the control system
- Convert digital speed and direction signals into analog voltages for the motors
In addition to these tasks, the leg control board must also provide a method of addressing the different devices onboard. The method of addressing devices is common to all expansion boards (or at least the method should be common; at this point the leg control board is the only expansion board that has been developed), but is discussed here for coherency.
The ribbon cable connects the 8-bit data bus and the 6-bit address bus from the SmartCore controller to the leg control module. A decoder on the module takes the address from the controller and selects the appropriate device to talk to the bus by enabling it. For example, if the controller wishes to turn on motor 1 as shown in Figure 16, it first places the address of the register attached to motor 1 on the address bus. The leg module decoder recognizes that address, and enables the latch connected to motor 1. Whatever control word is sent over the data bus is then routed to that latch. The control word specifies which direction the motor should turn, whether the brake is on or off and what speed the motor should turn at.
The leg control module can also send information back to the SmartCore controller. Information about the leg position is sent back by first decoding an analog signal from potentiometers attached to the leg into a binary word, and then placing the word on the data bus. The SmartCore requests this information by placing the address of the A-D (analog to digital) converter on the address bus. The leg controller’s device selector recognizes this address as belonging to the A-D converter, and it enables the converter’s output. Whatever digital word corresponds to the potentiometer setting is then placed on the data bus. The SmartCore can read this position off the data bus, and infer the position of the leg.
Additional tri-state buffers can send discrete on-off information to the embedded controller, such as limit switch states or contact sensor states. Only three inputs are shown for clarity, but there are actually 8 reserved discrete inputs per leg. There is a high limit and low limit switch input for each of three legs, and a contact sensor input for the foot, leaving one spare input.
Figure 16 - architecture of leg control board
4.2 Addressing Hardware Devices
Each hardware device used in this architecture is an 8-bit device. This means that when it is accessed, there are either 8 different bits to be written to, or 8 different bits to read from. Each one of these groups of eight bits resides on a single chip or integrated circuit, such as an 8-bit latch. Each one of these devices has an enable line so that multiple 8-bit devices do not try to use the data bus at the same time. There is never more than a single enable line active at a time in a single control segment (recall that a single control segment consists of a SmartCore board and all of the boards attached to it by a ribbon cable).
Each one of these enable lines has a unique address. In order to talk to hardware devices, the controller must first place the binary value of the enable line’s address on the address bus, and activate the appropriate chip select line. The hardware to achieve this is described in this section.
4.2.1 Memory Mapping with the 74LS138
Figure 17 - 74HC138
The 74LS138 is a 3-to-8 decoder chip (sometimes called a 1-of-8 decoder) used to decode an address and enable a specific device. It is shown in Figure 17. Pins 1-3 read the address, and the appropriate output is enabled. The chip also has two three enable inputs G1, G2A and G2B. G2A and G2B both must be low (logic 0 or 0V) in order to enable any of the outputs, and G1 must be high (logic 1 or +5V). The outputs are all normally high. When a particular output is selected, it goes low. For example, if the input logic levels to {A B C} were {0 0 0}, pin 15 would go low and the others would remain high, provided that G2 and G1 were both low and G1 was high.
If we connect this device up to the address bus, we can begin to build the address decoding sub-system. This configuration is shown in Figure 18. Here we have connected the 74HC138 to the first 3 bits of the address bus. Now we can decode a 3-bit address into 1 of 8 signals. Depending on the address specified, 1 of the 8 outputs on the 74HC138 will be low while all the others will remain high.
Figure 18 - initial address decoder
However, this is insufficient. First of all, we are only using 3 of a possible 6 address lines, so we are not utilizing the full addressable range of values. Also, what if we didn’t want to talk to any of the devices? In the configuration shown, 1 of the 8 outputs is always active. For the first problem, we can use a second 74HC138 and a set of jumpers to give the board a specific ID. For the second problem, we can use the chip select lines and another jumper block. This gives us our final address decoding subsystem as shown in Figure 19, which can be used on all of the expansion boards that address hardware in this manner.
Figure 19 - final address decoding subsystem
The chip select lines are used to "mask" hardware I/O events. JP1 is used to select which chip select is used on a particular board. Jumping pins 1-14 selects /CS1, jumping pins 2-13 selects /CS2, and so on. You can also disable the chip select function by jumping pins 7-8 on JP1. Recall that the chip select lines are active low, so the chip select chosen on JP1 connects directly to the active low input G2B on U2.
U1 is used to decode the most significant 3 bits of the address bus, and U2 is used for the least significant 3 bits. The output from U1 is sent through another jumper block, JP2. JP2 is used to select the "board ID" of the expansion board (this is analogous to choosing an IRQ value for ISA expansion cards on a PC computer). Each board connected to the same data and address bus must have a unique board ID and chip select combination. You can have up to 8 boards sharing the same chip select.
The entire addressing subsystem is represented by the "Decoder/Device Selector" block in Figure 16. The lines coming out of it go to different 8-bit devices. Whichever 8-bit device is selected is allowed to either read data from the data bus (if it is an output device), or put data onto the data bus (if it is a feedback channel).
A single leg control module has the capacity for 8 digital inputs, or 8 inputs per leg. These inputs are not currently implemented, but are intended to be used for reading limit switches or contact sensors attached to the legs. To place the information on the data bus, the 74HC245 chip is used. This device is shown in Figure 20.
Figure 20 - Tri-state octal bus transceiver
The direction bit controls the direction of information flow. Keeping this bit tied low makes data flow from B to A. Pin 19 is the enable bit. While high, the enable bit keeps the output register in the high impedance state. The device is enabled by setting the enable pin low. To do this, it is connected directly to an output line of the 74HC138.
When enabled, the digital word on the B-register is passed to the A-register. The A-register is connected directly to the data bus, which can then be read by the embedded controller. The B-register is connected to a series of switches. When the switches are open, the output from transceiver is set high. When closed, the switches set the inputs low.
Motors are high-powered components compared to devices in the digital world. The current draw of a typical digital latch such as those used in this project is around 0.3 mA. A digital output from such a device is capable of sourcing around 10-20 mA. A typical DC motor requires anywhere from 100 to 3000 mA. Clearly, in order to interface a digital circuit with a motor, some special hardware is needed.
One solution is the use of a circuit known as an h-bridge, named after its H-shaped configuration. The h-bridge circuit is shown in Figure 21. It uses four current amplifying power transistors to control the motor current. By activating a transistor pair, current is made to flow through the motor in a particular direction. The diagram on the left of Figure 21 shows the h-bridge configuration. By turning on the inputs labeled ‘A’, current is made to flow through the motor in the direction indicated by the A-A line. By turning on the other two inputs labeled ‘B’, current is made to flow in the opposite direction, as indicated by the B-B line.
Obviously, we would not want to turn both A and B on at the same time, or we would get a direct connection between ground and the supply current, causing a short circuit. In order to prevent this from occurring, we can add some control logic to the inputs. The Direction input controls which set of two transistor is turned on, and the On/Off input controls whether either pair of transistors is turned on.
Figure 21 - h-bridge circuit (left), and with logic control (right)
By connecting the two inputs to a digital control system, we have eliminated the current sourcing problem.
However, a new problem arises due to the voltage levels used. The digital logic levels used in TTL circuits ranges from 0-4.5V. This means that the inputs to the h-bridge circuit are limited to this range. However, the motor supply current reaches 12V. One of the characteristics of the power transistors shown in Figure 21 is that the voltage difference between the base and emitter (the middle pin and the pin with the arrow on it) must be at least 2.4V. This is not a problem for the two transistors on the bottom, since their emitter pins are connected to ground (0V). However, for the two transistors on the top, the emitter voltage is much higher, due to the large voltage drop across the motor. In fact, they exceed 6V, so the voltage difference between the base that is supplied by a 0-5V circuit and the emitter will never be great enough to turn the transistor on.
In order to solve this problem, a specialized circuit known as a charge pump can be used. This circuit amplifies the control voltage to the proper level using an oscillator and a capacitor pair. The LMD18200 device manufactured by National Semiconductor incorporates both the charge pump and the h-bridge circuit described. Some additional functionality is also provided by the device, including current sensing for stall detection, and a pulse-width modulation input for speed control. This device is used on the leg control module to control the power switching of the motors. Its operation is described in the next section.
4.4.1 The LMD18200 H-Bridge Chip
National Semiconductor’s LMD18200 h-bridge chip is a complete, if expensive, solution to motor control circuits. It is shown in Figure 22. Its flexible design allows for a number of different configurations. There are three control inputs; the brake, direction, and PWM input lines. These inputs accept digital logic level voltages and apply a corresponding current output at pins 2 and 10.
Pins 8 and 9 are not implemented in the current design. The current sense output is used to detect stall conditions at the load. If the motor is physically prevented from moving while it is turned on, the current going through the motor increases substantially. The current sense output detects this condition and outputs a voltage that is proportional to the amount of current going through the motor. This output was not used in the design because stall conditions can already be detected by the potentiometers at the leg joints. The thermal output is used for detecting a thermal overload condition. The chip has built in circuitry that shuts the motor down if the thermal limits of the device are breached. If this condition occurs, the thermal output line goes high. Because we are not operating the device anywhere near its thermal limits, this feedback signal is ignored in the leg module design.
Figure 22 - LMD18200 h-bridge device
The two bootstrap outputs are used if the rate at which the load is being turned on and off is very high, which is the case for certain applications like stepper motors. By using bootstrap capacitors, the rise time of the output signal can be reduced to 100 ns, and the switching frequency increased up to 500 kHz. The leg motors do not require high frequency switching, so the bootstrap lines are not used.
4.4.2 Generating Motor Control Signals
The motor control signals are generated by dedicated microprocessors. The detailed specification and code for these microprocessors is included Appendix D – PWM Specification. However, a brief description is given here.
A motor control register (PIC16C84 in Figure 23) is loaded with an 8-bit word from the microcontroller. This word contains a direction bit (D0), a brake bit (D1), and six speed bits (D2-D7) that specify the desired pulse-width for the PWM line. The motor control register interprets the command encoded in the 8-bit word, and sets the state of three output lines, - DIR, BRAKE, and PWM, - accordingly. These lines connect directly to the LMD18200T H-bridge motor driver for the particular motor. The leg control algorithms that attempt to move the foot of the leg through some trajectory determine the speed for each individual motor.
Figure 23 - motor control circuit
There are some other notable features in the circuit shown in Figure 23. The resistor-capacitor-diode network near the bottom of the schematic is connected to the reset signal on the PIC16C84. This circuit is suggested in the data sheet for the PIC16C84 from Microchip Technologies. It prevents the microprocessor from resetting due to temporary brownouts on the power line. When the power is removed (or turned off), the diode allows the capacitor to discharge quickly and the microprocessor resets normally.
Another notable feature is the pair of capacitors attached to the power and ground pins on the LMD18200. These are decoupling capacitors that prevent a loss of power on the chip, particularly when a motor is switched from an off state to a full on state. This large instantaneous load will cause power spikes on the power grid. The decoupling capacitors work to minimize the amplitude of the spike and maintain power.
The last feature is the oscillator at the top of Figure 23. This is used in place of a crystal-capacitor network to generate clean clock signals at a frequency of 8 MHz. The PIC16C84 can operate at clock frequencies from DC to 10 MHz [21] .
Some example eight bit words and the resulting outputs from the motor control register are shown in Table 1.
Pulse-Width setting bits
DIR
D7
D6
D5
D4
D3
D2
D1
D0
HEX
Description
Table 1 - sample motor control register values
Figure 24 shows how the output lines from the motor control register are set if the values from Table 1 are loaded into the register. At the far-left of the diagram, the power up configuration is shown in which the DIR, BRAKE, and PWM lines are all set high. The register is then loaded with the value $FD. This turns off the brake and sets the PWM line at 100% duty cycle (maximum speed). Next $C8 is loaded, which switches the direction of the motor and reduces the duty cycle to 80%. The next two values $7C and $60 maintain the direction of the motor but reduce its duty cycle to 50% and 20% respectively.
Figure 24 - sample motor control register outputs
It is important to realize that there is a lag between the time the enable line is asserted and the time the microprocessor code is able to read the value on the data bus. When the enable line triggers an interrupt signal, the microprocessor must first save the program counter and the state of its internal registers, and then it can process the interrupt. This causes a problem if the value on the data bus has changed by the time it can be sampled by the PIC16C84. This problem was encountered during early development of the motor control board, because the I/O cycles on the SmartCore microcontroller are faster than the time it takes for the PIC16C84 to prepare for processing the interrupt. For this reason, an 8-bit latch must be used to latch the value on the data bus, so that it can be stored long enough for the PIC16C84’s to see it. This register is visible in the final schematic, with the label U13. This register updates its value every time the motor board is accessed by a chip select signal (regardless of whether the I/O signal is a motor control command or not).
4.5 Analog to Digital Conversion
The main feedback channel for the legs is through potentiometers located at each of the three joints. The potentiometers output a voltage between 0-5V proportional to the angle of the shaft. In order to convert this voltage level to a format that is readable by the embedded controller, an analog to digital conversion must be performed.
In order to pick an appropriate analog to digital converter (ADC), the requirements must be clearly specified. Because we are using an 8-bit data bus, and we do not require any greater resolution than 28 = 256 measurable positions at each of the joints, we will limit our selection to 8-bit parallel bus ADC’s.
Each joint in the leg is physically limited to <180° of rotation. A standard potentiometer rotates a full 270°, which means that the full voltage range from 0-5V can not be used (see Figure 25).
Figure 25 - Potentiometer: mechanical (left) and electrical (right) representation
To calculate the angular resolution of the measurement, we have:
270 [degrees] / 256 [bits] = 1.05 [degrees / bit] = 1 [index]
By factoring in the maximum angular velocity of the leg motor, we can determine how many index points are passed per second. Software simulations of the leg mechanics suggest that it is unlikely to expect a leg joint rotation greater than 120 [degrees / sec], which corresponds to a rotation rate of 20 [RPM]. So we have:
120 [degrees / sec] / 1.05 [degrees / bit] @ 114 [bits / sec] = 114 data changes per second = 114 [Hz].
In order to sample this data properly, we use the Nyquist sample rate, which says that the sample frequency must be at least twice the rate of the signal being sampled.
Sample frequency = 2* (frequency of data to be sampled) = 2 * 114 = 228 Hz.
Note that this sample rate is for a single analog input. If we wish to sample more than one joint, i.e. if we wish to move more than one joint at a time, we have to multiply the sample frequency accordingly. The number of joints that are in motion at any time depends entirely on the walking gait. We do not wish to limit the number of joints that can be in motion at any particular time. For this reason, we will say that we want to sample the analog inputs quickly enough so that all six motors controlled by the leg controller module can be in motion at the same time. For an added factor of safety, we round up the sample rate per joint to 250 Hz. The required sample rate is now:
6*250 Hz = 1.5 kHz, which corresponds to a conversion time of 1/1.5 [kHz] @ 667 ms
So if we select an ADC device with a conversion rate < 667 ms, we will be able to sample the position of all of the joints accurately.
The ADC0801, as shown in Figure 26, is well suited to the ADC requirements of the leg controller module. It has a conversion time of 100 ms, well within the operational requirements of the controller. It has a tri-state 8-bit parallel bus output, which is perfectly suited to the existing bus architecture of the controller. Because of the nature of the ADC0801’s control lines, it can operate either synchronously (under handshaking control of the microprocessor, which ensures no data conversion errors occur) or asynchronously (no handshaking with the microprocessor, which simplifies both the hardware and software implementation).
Asynchronous operation is achieved by connecting the EOC output directly to the Start input, so that every time an End Of Conversion signal is asserted, a new conversion is triggered. This ensures that the 8-bit word appearing on the data bus is always the most current conversion value. This is the method that is used in the controller.
The ADC0801 uses a successive approximation register to complete the conversions. These conversions are clock driven by an external clock input. The clock frequency must be in the range 10-1280 kHz according to the device specifications. Because the conversion time is related to the clock frequency, we want a clock frequency near the upper limit of this range. The nominal frequency that gives us a conversion time of approximately 100 ms is 640 kHz.
A crystal oscillator is used to provide this clock pulse. Crystal oscillators have the desirable attribute of extremely precise and noise-free clock signals. In the leg control module, a 1.19 MHz oscillator is used to generate the clock pulses for the ADC0801’s. A single oscillator is shared between the three required ADC0801’s.
Each potentiometer has a dedicated single channel ADC0801. The microcontroller can sample these channels as fast as it is capable and never obtain a reading that is more that 100 m s old.
Figure 26 - A2D channel
Trim pots were added to the voltage references on each of the A2Ds, to allow "windowing" of the voltage range. This is an improvement over an earlier design that would always assume an input voltage range between 0V and 5V, as shown in Figure 27 (a). The trim pots allow for narrowing the input voltage range to any arbitrarily narrow range, illustrated in Figure 27 (b). This improves the resolution of the measurements of the potentiometer voltages, which typically vary between 1.2V and 4.5V in a full sweep of the leg’s work envelope. Figure 27 shows an example of a potentiometer value varying between a maximum value of 3.7 volts and a minimum value of 1.5 volts.
Figure 27 - sampling a signal with (b) and without (a) trim pot adjustments
The minimum voltage is adjusted with trim pot R2 in Figure 26, and the maximum sampling voltage is adjusted with trim pot R1 in Figure 26. The analog signal input arrives on pin 6 (VI+), and the digital word is read from pins 11-18 (DB0-DB7) when the /RD line goes low (pin 2).
When the motor control boards are initialized, the analog to digital conversions must be "tickled" in order to guarantee they start the conversion process. As mentioned earlier, the ADC0801’s can be put into a continuous conversion mode by tying the /INTR output to the /WRT line, but this line must initially be set high. The circuit that accomplishes this is shown in Figure 28.
Figure 28 - reset circuit
When the chip enable line (labelled Y7) is asserted by the SmartCore microcontroller, the CLK2 signal (attached to the same 1 MHz clock feeding the ADC0801’s) is connected to the pins labelled AD<n>_RESET. These reset lines are in turn connected to the /INTR-/WR pins on the ADC0801’s. This places an oscillating signal on the /INTR-/WR pins, which in turn starts the initial conversion process.
At the same time that the ADC0801’s are reset, the PIC16C84’s are reset as well. The resistor-capacitor-diode network mentioned in section 4.4.2 is visible here. Now however, the reset line is also connected to pin 2. When the chip enable line is asserted, A1 connects to B1, which in turn grounds the reset line. This will also reset the PIC16C84’s.
When the chip enable line is not asserted the entire U9 device appears logically invisible to the circuit as it is in the high-impedance state.
Each IC on the motor control board has at least one decoupling capacitor, usually with a value of 0.01 m F. These decoupling capacitors help to maintain current in the devices they are mounted beside during high frequency logic switching. They achieve this by reducing the effective supply and return impedance. Note that their location on the schematic has no physical relevance; it is up to the PCB designer to mount these decoupling capacitors as close as possible to the power connectors for the logic devices with which they are associated. For a good discussion of the theory behind the use of decoupling capacitors, see [21] section 2.4.
4.6.3 Terminating Unused Inputs
All unused inputs on the motor control board should be tied low to avoid problems with floating inputs affecting other logic devices in the same package. The unused inverters from U14 and figure 56. are all tied to ground for this reason, for example.
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page. Last updated: April 20th,
1997
